Re: [Jack-Devel] ALSA PCM multi plugin and xruns

On Tue, 11 Dec 2012 21:05:39 +0000 John Rigg <[hidden]> wrote:
> On Tue, Dec 11, 2012 at 08:52:56PM +0000, John Rigg wrote:
> > Yes. Sync is achieved by using a phase-locked loop (PLL). It's
> > either locked completely or not at all. The PLL typically runs at
> > 128 or 256 x fs, so even if it takes a few tens of cycles to lock
> > after startup, it synchronises pretty quickly compared with the
> > word clock period.
> Correction: time taken to achieve lock can be significantly longer
> than the word clock period (my PLL theory is a little rusty). On a
> system where all cards are driven by a common clock this shouldn't be
> an issue, but it still doesn't cure the problem being discussed.

Its even the other way around: The PLL has to adopt to changes rather
slowly. Otherwise the smallest jitter in the word-clock would make your
PLL run wild. But a slow PLL calls for a long time to sync.

Have fun,

Arnold

1355269786.25342_0.ltw:2, <20121212004937.72047c66 at saratoga dot arnoldarts dot de>