Re: [Jack-Devel] ALSA PCM multi plugin and xruns

On Tue, Dec 11, 2012 at 08:52:56PM +0000, John Rigg wrote:
> Yes. Sync is achieved by using a phase-locked loop (PLL). It's either locked
> completely or not at all. The PLL typically runs at 128 or 256 x fs, so
> even if it takes a few tens of cycles to lock after startup, it synchronises
> pretty quickly compared with the word clock period.

Correction: time taken to achieve lock can be significantly longer than the
word clock period (my PLL theory is a little rusty). On a system where
all cards are driven by a common clock this shouldn't be an issue,
but it still doesn't cure the problem being discussed.

John

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