Re: [Jack-Devel] ALSA PCM multi plugin and xruns

On Wed, Dec 12, 2012 at 12:49:37AM +0100, Arnold Krille wrote:
> On Tue, 11 Dec 2012 21:05:39 +0000 John Rigg wrote:
> > On Tue, Dec 11, 2012 at 08:52:56PM +0000, John Rigg wrote:
> > > Yes. Sync is achieved by using a phase-locked loop (PLL). It's
> > > either locked completely or not at all. The PLL typically runs at
> > > 128 or 256 x fs, so even if it takes a few tens of cycles to lock
> > > after startup, it synchronises pretty quickly compared with the
> > > word clock period.
> > Correction: time taken to achieve lock can be significantly longer
> > than the word clock period (my PLL theory is a little rusty). On a
> > system where all cards are driven by a common clock this shouldn't be
> > an issue, but it still doesn't cure the problem being discussed.
> 
> Its even the other way around: The PLL has to adopt to changes rather
> slowly. Otherwise the smallest jitter in the word-clock would make your
> PLL run wild. But a slow PLL calls for a long time to sync.

Yes, I was obviously sleep-deprived when I made that comment about
PLLs locking quickly. In high quality audio interfaces it's common
to use two PLL stages, one to lock to the incoming clock and a
second one (often a VCXO) for jitter attenuation.

John

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