Re: [Jack-Devel] Ethernet-based audio interface using (net)jack idea

 Fons,

 The clock generated by the DPLL is not intended as the sampling clock:


> > and feeding that signal back
> > (externally - FPGA PLL inputs are always dedicated inputs) into one of
> the
> > FPGA PLLs to generate MCLK.
>

In fact, my idea was to use one of the FPGA analog PLLs with slow loop
setting to lock onto the
jittery (but not as jittery as the sync packets) DPLL output. So I will be
using the FPGA analog PLL as a VCO.

The main question remains whether or not the PLL will be able to properly
lock on a DPLL output signal that is - indeed - fairly jittery. That
probably calls for an experiment.



> I seriously doubt if you can get a sampling clock with the required
> low jitter using the FPGA's digital PLLs. The next thing to look at
> would be an external VCXO module to generate the master clock, with
> the loop closed by digital filtering in the FPGA followed by an
> analog lowpass driving the VCXO. Lock range for VCXOs is small but
> it should be enough to cover typical sound card frequency
>
>
What jitter performance would actually be required by pro-audio ?

J.



> Ciao,
>
> --
> FA
>
>

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