Re: [Jack-Devel] Ethernet-based audio interface using (net)jack idea

On Mon, Aug 15, 2011 at 11:03:15PM +0200, Jeroen Van den Keybus wrote:
 
> It think this may eventually end up by you generating a square wave
> synchronous to the Jack server sync packets, and feeding that signal back
> (externally - FPGA PLL inputs are always dedicated inputs) into one of the
> FPGA PLLs to generate MCLK. Beware that the square wave will really need to
> be 'good' in a sense that simply clocking the FPGA PLL with sync pulses will
> not do (too low a frequency - too much jitter). Therefore you will need a
> digital PLL (= VHDL file) first. Beware that clock generation in this
> fashion isn't common at all (let alone recommended), but since it would save
> so much trouble processing the data, I think it's worth trying...

I seriously doubt if you can get a sampling clock with the required
low jitter using the FPGA's digital PLLs. The next thing to look at
would be an external VCXO module to generate the master clock, with
the loop closed by digital filtering in the FPGA followed by an
analog lowpass driving the VCXO. Lock range for VCXOs is small but
it should be enough to cover typical sound card frequency 

Ciao,

-- 
FA

1313519247.3714_0.ltw:2,a <20110816182703.GA22182 at linuxaudio dot org>