Re: [Jack-Devel] Ethernet-based audio interface using (net)jack idea

I've been reading the manual for the Altera DE1 board, and given its
expense, would it be worth looking into finding a used one to work with on
this project? I appears to have two clock sources of its own (27 and 50MHz),
and the expansion connectors would provide me with (more than enough) the
inputs we'd require to connect from the ADC. Maybe, if the clocks on the dev
board are good enough, we could use those in our project-specific version of
the circuit.

It also has an array of LEDs and 7-segment displays, so there's the option
of programming activity lights and numerical read-outs (for the sample rate,
for example) further down the line.

I keep watching youtube videos on the Quartus software, and it looks more
and more appealing to program this way. I suppose I need to start saving up!

However, there is also the Xilinx-based board that Jeri recommended to me in
the first instance (the Avenet LX9 micro board) is a lot cheaper, but
because everyone has been discussing mainly the Altera products, I've not
looked into their feasibility, and whether they would be more or less
difficult to work with than the Cyclone boards. Their cost is less, so it's
still something I've been considering.

I'll continue to look for sources on good clock sources, but thanks everyone
so far for the discussions and the experience!

Dan

On Thu, Aug 18, 2011 at 11:40 AM, Fons Adriaensen <[hidden]>wrote:

> On Wed, Aug 17, 2011 at 12:41:00PM +0200, Jeroen Van den Keybus wrote:
>
> > In fact, my idea was to use one of the FPGA analog PLLs with slow loop
> > setting to lock onto the
> > jittery (but not as jittery as the sync packets) DPLL output. So I will
> be
> > using the FPGA analog PLL as a VCO.
> >
> > The main question remains whether or not the PLL will be able to properly
> > lock on a DPLL output signal that is - indeed - fairly jittery. That
> > probably calls for an experiment.
>
> That indeed remains to be seen. You can probably make it lock, the
> question is what BW it requires.
>
> Anyway creating a master sample clock from low frequency sync
> messages using a PLL is not easy. But since you have the computing
> power of an FPGA at your disposal there are alternatives in the
> form of open-loop solutions.
>
> Put a timestamp (using the current clock) on the sync messages,
> unwrap any modulo on the time stamps and perform a linear
> regression on a few hundred of them - this is equivalent to
> filtering in a PLL but doesn't have the stability problems
> as it is open loop. Repeat for each incoming sync packet,
> low-pass filter the result to drive a VC(X)O.
>
> Ciao,
>
> --
> FA
>
> 
> Jack-Devel mailing list
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>

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